The present invention is related to error detection in data transmission systems, and particularly to the concurrent calculation of cyclic redundancy checks (CRCs) from different channels or of different messages.
The purpose of error detection systems is to detect whether data messages are corrupted during transmission. If the presence of one or more errors is detected in a received data message, the data message can either be ignored, for example in voice and video applications, a retransmission can be requested, for example in Ethernet and other types of data communication systems, or the error can be corrected, as in forward error correction systems. Being able to detect errors, whether or not the errors are corrected, means that the introduction of errors does not have the same implication as if the errors go undetected, that is, it is not as important to avoid the occurrence of errors if they can be detected. This allows data network systems to be designed such that errors are allowed to occur, typically so long as they occur at or below a known manageable rate. The result is that data can be transmitted at a lower power level and at higher transmission rates. Because of this, data can be transmitted farther and channel capacity can be increased.
Modern data networks transmit data at ever higher data rates, thus received data needs to be processed quickly. Accordingly, the trend in cyclical redundancy checking is to process more bits of data simultaneously. Additionally, modern data networks transmit different messages over the same physical line, where each message may correspond to a different sender or channel. These different messages may be arrive at the CRC circuitry in packets that are interspersed amongst each other. Traditional approaches duplicate the circuitry for different channels, which increases the complexity and cost of the circuitry. Other approaches may drain the circuitry of data for one channel and then restart a computation of another channel, but this is computationally slow.
Therefore, it is desirable to have circuits, methods, and apparatus for rapidly handling interspersed packets from different messages without greatly increasing the complexity of the circuitry required to process them.